1. Field of the Invention
This invention relates to a ferroelectric memory and a test method thereof and more particularly to a memory which consists of series connected memory cells each having a transistor (T) having a source terminal and a drain terminal and a ferroelectric capacitor (C) in between the two terminals, hereafter named “series connected TC unit type ferroelectric RAM”.
2. Description of the Related Art
Recently, ferroelectric memory has rapidly developed. Although the memory is of a nonvolatile type, it has an advantage over a flash memory which is also a nonvolatile device in that the number of rewritable operations is large, the programming time is short and operation with the low voltage/low-power consumption can be performed.
However, when the device is compared with a DRAM, the device has a disadvantage that the cell size cannot be made smaller than 8F2 (F is the minimum line width determined by the design rule) because the device is formed with the folded bit line structure and the operation speed is lower than that of the DRAM since it is necessary to drive a plate line having large capacitance.
Therefore, in order to solve the above problems, the “series connected TC unit type ferroelectric RAM” was proposed in VLSI Circuit Sympo. 1997 pp. 83 to 84 “High-Density Chain Ferroelectric Random Access Memory (CFRAM)” and ISSCC Tech. Dig. Papers, pp. 102 to 103, February 1999 “A Sub-40 ns Random-Access Chain FRAM Architecture with 7 ns Cell-Plate-Line Drive”. It is described in the above reports that higher speed operation and higher integration density can be attained in comparison with an FeRAM which is conventionally known since the cell size is half that of the latter and the bit line capacitance is ¼ times that of the latter.
However, when the series connected TC unit type ferroelectric RAM performs the operation shown in the following table 1, a potential difference, that is, a disturbance occurs between two ends of each memory cell capacitor so as to reduce the remnant polarization amount.
TABLE 1Word LinePlate Drivingto beSystemSelectedOperationSingle PlateWL<0>Program “1” fromPulse Systemoutside the chipafter data “0”is read out
FIG. 1 is a schematic configuration diagram showing a series connected TC unit type ferroelectric RAM which was formed before the solution to the above problem was made according to the prior Japanese Patent Application (Jpn. Pat. Appln. KOKAI Publication No. 2000-339973) by the inventors of this application and others. In FIG. 1, an extracted part of the memory cell array and peripheral circuit is shown.
That is, in FIG. 1, memory cell units are arranged in matrix form in a memory cell region. Each memory cell unit is formed by serially connecting a plurality of memory cells which are each formed by respectively connecting two electrodes of a ferroelectric capacitor to source and drain terminals of an enhancement type (E type) N-channel MIS transistor.
In this example, two memory cell units which are respectively formed of series-connected eight memory cells M0 to M7 and BM0 to BM7, for example, are typically shown. The cells M0 to M7 are respectively formed of transistors Tr0 to Tr7 and capacitors C0 to C7 and the cells BM0 to BM7 are respectively formed of transistors BTr0 to BTr7 and capacitors BC0 to BC7.
The gate electrodes of the transistors Tr0 to Tr7, BTr0 to BTr7 are respectively connected to corresponding word lines WL<0> to WL<7>. Further, one end of the memory cell unit is connected to a plate line PL<0> or PL<1> and the other end thereof is connected to a bit line BL or bit line BBL which is complementary to the bit line BL via a block select MIS transistor (block selector) QB0 or QB1.
Further, the bit lines BL, BBL are connected to a sense amplifier region 10. In the sense amplifier region 10, an equalization circuit EQ, flip-flop type sense amplifier SA, column select gate CG and the like are formed.
The block select MIS transistors QB0, QB1 are respectively controlled by block select signals V(BS<0>), V(BS<1>). The equalization circuit EQ is controlled by an equalization control signal V(BEQL). The sense amplifier SA is controlled by sense amplifier activation control signals V(SEN), V(BSEP). Further, the column select gate CG is controlled by a column select signal V(CSL).
The timing chart of FIG. 2 shows the program operation of the device with the configuration shown in FIG. 1 in which a single plate pulse system realized in a two transistor-two capacitor (2T2C) configuration is used and data “1” is programmed from outside the chip after the word line WL<0> is selected to select the memory cell M0 and read out data “0” as the conventional program operation.
More specifically, first, after the potential level of the equalization control signal V(BEQL) is lowered to release the equalized state of the paired bit lines BL and BBL, the driving potential V(WL<0>) of the word line WL<0> is lowered to select a 0th word line (at the end of the operation, the word line driving potential V(WL<0>) is raised). Then, the potentials of the plate lines PL<0>, PL<1> are raised to raise the plate line potentials V(PL0, PL1) and read out the polarization of the memory cell onto the bit line pair BL, BBL in the form of charge. Next, the sense amplifier activation control signals V(SEN) and V(BSEP) are respectively set to high and low levels to activate the sense amplifier SA and compare and amplifier potential difference occurring between the paired bit lines BL and BBL. At this time, the polarization of the capacitor C0 in the memory cell M0 is set in a direction toward the sense amplifier SA from the plate line PL<0>, that is, data stored in the memory cell M0 is “0”. Therefore, as the result of comparison and amplification, the potentials of the nodes N<1> to N<7> are the plate line raising potentials and the potential of the node N<0> is 0 V. After this, the column select line SL is selected with the sense amplifier SA kept activated and “1” data is programmed from the data line pair DQ, BDQ via the DQ gate QG. Then, as shown in FIG. 3, when the word line raising potential is low, the potentials of the nodes N<1> to N<7> are largely booted, and at the same time, potential differences occur between the nodes N<7> and N<6>, nodes N<6> and N<5>, nodes N<5> and N<4>, nodes N<4> and N<3>, nodes N<3> and N<2>, and nodes N<2> and N<1>. The reason for this is explained below.
Since the potential is further booted from the plate line raising potential by the sense amplifier SA, the cell transfer gates Tr0 to Tr7 are turned OFF because of the rise in the threshold voltages due to the substrate bias effect. Since the potential is further booted by the sense amplifier SA after they are turned OFF, a portion amplified after they are turned OFF is capacitively divided by capacitive components connected between the sense amplifier SA and the cell transfer gates which are turned OFF. As a result, a potential difference occurs across each cell transfer gate and acts as a disturbance which reduces the remnant polarization amount.
According to the waveform diagram shown in FIG. 3, it is understood that large potential difference (disturb) occurs, particularly, between the nodes N<2> and N<1>. At this time, if the polarization of the capacitor C1 in the non-selected memory cell M1 is set in a direction toward the sense amplifier SA from the plate line PL<1>, that is, data stored in the non-selected memory cell M1 is “0”, an electric field which reduces the remnant polarization amount is applied. It is specifically described in the prior Japanese Patent Application (Jpn. Pat. Appln. KOKAI Publication No. 2000-339973) that disturbance will occur in cases as shown in the following table 2 and table 3 in an operation other than the operation described above.
TABLE 2Plate DrivingWord Line to beSystemSelectedOperationDouble PlateWL<0>Program “1”Pulse Systemfrom outsidethe chip afterdata “0” isread out
TABLE 3Plate DrivingWord Line to beSystemSelectedOperationDouble PlateWL<7>When dataPulse System“1” is readout
The following countermeasure is proposed in the prior Japanese Patent Application (Jpn. Pat. Appln. KOKAI Publication No. 2000-339973) to solve the above problems.
FIG. 4 is a circuit diagram showing the schematic configuration of a “series connected TC unit type ferroelectric RAM” designed to solve the above problems. FIG. 5 is a timing chart for illustrating a series of readout operation and program operation from outside the chip in a single plate pulse system and a waveform diagram showing detail transition of the potentials of the respective nodes shown in the memory cell region of FIG. 4 at the time of the above operations.
In this example, a case wherein the word line WL<0> is selected in a two transistor-two capacitor system is considered. Further, assume that the polarization which is set in a direction toward the bit line BL from the plate line PL<0> occurs in the capacitor C0 of the memory cell M0 which lies on the bit line BL side among the cells selected by the word line, that is, data “0” is programmed in the cell M0 and the polarization which is set in a direction toward the plate line PL<1> from the bit line BBL occurs in the capacitor BC0 of the memory cell BM0 which lies on the bit line BBL side, that is, data “1” is programmed in the cell BM0. In this example, a case wherein data “0” is read out from the memory cell M0 and then data “1” is programmed from outside the chip is explained below.
The operation of the above circuit is specifically explained below with reference to FIG. 5. First, the equalization control signal V(BEQL) is lowered to a low level to release the equalized state of the paired bit lines BL and BBL and make preparation for readout of data onto the bit lines. Next, the potential of the word line WL<0> is set from a high level (VPP) to the low level (0 V) to make preparation for application of potential difference between two ends of the cell. After this, the block select signals V(BS<0>, V(BS<1>) are raised from the low level (0 V) to the high level (VPP) so as to raise the plate lines (PL<0>, PL<1>) from the low level to the high level and consequently read out data onto the paired bit lines BL, BBL.
Next, φt gates (separation transistors) QS are turned OFF by setting a separation control signal φt to the low level (0 V) from the high level (VPP) so as to separate portions of the paired bit lines BL, BBL in the memory cell array region from portions thereof in the sense amplifier region. In this state, the sense amplifier activation signals V(SAN), V(SAP) are respectively set to the high and low levels to perform the sense and amplification operation. While the separation operation is being performed, the potential V(CSL) of a column select line CSL is raised to read out data to outside the chip or program data from outside.
Data “0” is programmed into both of the memory cells M0 and BM0 by equalizing the paired bit lines BL, BBL to 0 V after the φt gates QS are turned OFF, that is, the direction of the polarization of the capacitors C0 and BC0 is set in a direction toward the bit line from the plate line. Then, the plate line potentials V(PL<0>, V(PL<1>) are set to 0 V to release the equalized state and set the paired bit lines BL, BBL into an electrically floating state again. After this, data latched in the sense amplifier SA is programmed onto the paired bit lines BL, BBL by turning ON the φt gates QS. At this time, if the potential of a portion of the sense amplifier region 10 which lies on the bit line BL side is set at the high level, polarization set in a direction toward the plate line from the bit line is newly programmed (the direction of the polarization is set again), but if the potential is set at the low level, data which is first programmed and set in a direction toward the bit line from the plate line is kept programmed as it is (the direction of the polarization is kept unchanged). In this example, the polarization set in a direction toward the plate line from the bit line is programmed in the capacitor C0 of the memory cell M0 and data set in a direction toward the bit line from the plate line is kept programmed as it is in the capacitor BC0 of the memory cell BM0. Therefore, both of the plate line and bit line will not simultaneously set at the high level and the problem described before will not occur. Further, the effect that imbalance of the cell capacitor is prevented from appearing can be attained by performing the sense and amplification operation after the φt gates QS are turned OFF.
In the above explanation, a two transistor-two capacitor configuration is used, but in the case of one transistor-one capacitor (1T1C) operation, it can be easily attained by activating the plate line PL<0> or PL<1> and the block select signal V(BS<0>) or V(BS<1>) and separately creating reference potential. The countermeasure for the operations of the table 2 and table 3 is described in detail in the prior Japanese Patent Application (Jpn. Pat. Appln. KOKAI Publication No. 2000-339973).
However, the “series connected TC unit type ferroelectric RAM” described in the above prior Japanese Patent Application has some room for further improvement as described below.
(#1)
If the readout/inverted data program operation is repeatedly performed as described above in order to make a fatigue test for a ferroelectric capacitor of a cell, it takes a long time to control the sense amplifier and φt gates. Therefore, it is impossible to make an evaluation in a short time.
(#2)
When a reduction in the polarization amount due to disturb which occurs one time or plural times in a non-selected cell is tested and if the readout/inverted data program operation is repeatedly performed while the φt gates are kept in the ON state, it takes a long time to control the sense amplifier. From this point of view, it is impossible to make an evaluation in a short time.
(#3)
The potential of the word line WL<0> is lowered at the start time of the operation and raised at the end time of the operation. At this time, an electric field set in a direction toward the bit line from the plate line occurs at the operation start time as indicated by ΔC in FIG. 5 in the ferroelectric capacitor of the non-selected memory cell M1 or BM1 by coupling between the word line WL<0> and an electrode which lies near the plate line of the non-selected memory cell M1 or BM1. Further, an electric field set in a direction toward the plate line from the bit line occurs at the operation end time as indicated by ΔD. If polarization in the direction toward the bit line from the plate line previously occurs in the capacitor C1 of the non-selected memory cell M1 and polarization in the direction toward the plate line from the bit line previously occurs in the capacitor BC1 of the non-selected memory cell BM1, disturbance occurs in the cell BM1 at the operation start time and in the cell M1 at the operation time and there occurs a possibility that the polarization amount may be reduced.
In addition, if the readout/program operation is performed by one time or plural times, disturb to the adjacent cell M1 or BM1 due to a lowering/rise in the potential of the word line WL<0> cannot be evaluated in a short time.
(#4)
A case wherein the word line WL<0> is selected is considered. FIG. 5 is a timing chart and waveform diagram corresponding to FIG. 4 when the word line WL<0> is selected. Assume that polarization in a direction toward the plate line from the bit line previously occurs in the capacitor BC1 of the cell BM1, that is, data “1” is programmed in the cell BM1. When the potentials of the plate lines PL<0>, PL<1> are raised from the low level to the high level after the potential of the word line WL<0> is lowered at the time of the readout operation, a potential difference occurs between two electrodes of the ferroelectric capacitor BC1 of the cell BM1 due to the presence of the ON-resistance of the cell transistor BTr1 and the capacitive components of the cells BM1 to BM7. As a result, the polarization in the direction toward the plate line from the previously programmed bit line, that is, disturbance with respect to the data “1” occurs and there occurs a possibility that the polarization amount may be reduced.
Further, if the readout/program operation is performed by one time or plural times, a reduction in the polarization amount due to disturb applied to the cell BM1 when the potentials of the plate lines PL<0>, PL<1> are raised from the low level to the high level cannot be evaluated in a short time.
(#5)
A case wherein the word line WL<7> is selected is considered. Assume that polarization in the direction toward the bit line from the plate line occurs in the capacitor C6 of the cell M6, that is, data “0” is programmed in the cell M6. When the potential of the bit line is raised from the low level to the high level after the potential of the word line WL<7> is lowered at the time of the readout operation, a potential difference occurs between two electrodes of the ferroelectric capacitor of the cell M6 due to the presence of the ON-resistance of the cell transistor Tr6 and the capacitive components of the cells M0 to M6. As a result, the polarization in the direction toward the bit line from the previously programmed plate line, that is, disturbance with respect to data “0” occurs and there occurs a possibility that the polarization amount may be reduced (refer to ΔA, ΔB in FIG. 5).
Further, if the readout/program operation is performed by one time or plural times, a reduction in the polarization amount due to disturbance applied to the cell M6 when the potential of the bit line is raised from the low level to the high level cannot be evaluated in a short time.
Therefore, in order to solve the above problems, it is desired to further improve the series connected TC unit type ferroelectric RAM.